Many electronic devices are provided in an array form, including memories which have a plurality of addressable rows. Some arrays include redundant elements. For example, a memory intended to provide 256 selectable rows may be fabricated with one or more extra or redundant rows. This is done in order that a redundant row can be substituted for a defective row, so that the array can continue to be used and replacement of the entire device can be avoided. Portions of the array, such as rows of a memory, are typically selected using a decoder coupled to each selectable row. Each decoder has the functionality of a multi-input, single-output logic gate. Conceptually, a decoder can be viewed as an AND gate which will output a "high" select signal when all of the inputs received from an address bus are simultaneously high. For those decoders that are intended to select in response to an address which does not have all inputs high, the inputs which should be low in order to select the corresponding output line can have an inverter interposed.
In one common configuration, the decoder is a CMOS NAND gate with the output of the NAND gate provided to an inverter so that the low level select output is converted to a high level select output. Of course, other configurations are also used for decoders including configurations where the output line is selected by having a low level rather than high level or where an address input is active low rather than active high. These variations, and the apparatus used to achieve them, are well known to those skilled in the art.
When decoders are used in a device having redundant elements, a circuit is used to prevent the selection of a defective row in response to the address which would normally select such a defective row. Often this element includes a fuse which can be blown to provide an open line, with the fuse being blown by, for example, a laser or the input of high-amperage current.
Previous fused decoders have been fabricated using CMOS technology, i.e., have included circuitry in which providing the select signal requires both a PMOS and an NMOS transistor to respond to each bit of the input address. An example of such a device is described in U.S. Pat. No. 4,829,481 issued May 9, 1989 to Johnson, et. al. Although this device is useful for some purposes, the CMOS circuitry presents a large load to the address lines, particularly when the address bus has many address lines, such as 20 or more address lines (i.e., 20 or more address bits are input to the decoder).
Accordingly, it would be useful to provide a fused decoder such as can be used in conjunction with disabling a decoder output to permit selection of a redundant circuit, but having a reduced load presented to the coded address lines.